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Bit
Name
Reset
Access
Description
Set when the value written to LETIMERn_COMP0 is being synchronized.
1
CMD
0
R
LETIMERn_CMD Register Busy
Set when the value written to LETIMERn_CMD is being synchronized.
0
CTRL
0
R
LETIMERn_CTRL Register Busy
Set when the value written to LETIMERn_CTRL is being synchronized.
21.5.15 LETIMERn_ROUTE - I/O Routing Register
Offset
0x040
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:10
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1
(p. 3)9:8
LOCATION
0x0
RW
I/O Location
Decides the location of the LETIMER I/O pins
Value
0
1
2
3
Mode
LOC0
LOC1
LOC2
LOC3
Description
Location 0
Location 1
Location 2
Location 3
7:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1
(p. 3)1
OUT1PEN
0
RW
Output 1 Pin Enable
When set, output 1 of the LETIMER is enabled
Value
0
1
Description
The LETn_O1 pin is disabled
The LETn_O1 pin is enabled
0
OUT0PEN
0
RW
Output 0 Pin Enable
When set, output 0 of the LETIMER is enabled
Value
0
1
Description
The LETn_O0 pin is disabled
The LETn_O0 pin is enabled
2011-04-12 - d0001_Rev1.10
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